A Comparative VLSI Synthesis of Finite FieldMultipliersChristof

This contribution describes a comprehensive comparison of bit parallel nite eld multipliers. Four diierent multipliers in standard, dual, and normal base together with a relatively new approach which uses composite elds are compared. Four diierent eld orders from 2 8 to 2 32 are investigated. A high practical relevance is assured by using a highly automated design process and sea-of-gates chip in 0.8m technology as target hardware. The synthesis tool Synopsys is used for mapping and optimization. Unlike previous studies, quantitative results with respect to area and time performance are achieved. It is found that the new architecture requires the smallest number of gate equivalences. Dual and standard base multipliers require 30{40% more gates but have a somewhat smaller delay. The normal base multiplier has by far the highest gate consumption. It is concluded that the theoretical gate count is a valid estimate for the area requirement.